As a process for forming interconnects in a semiconductor device, there has been known a dual damascene process that forms grooves (also called “trenches”) for embedding wirings of Nth level and via holes for embedding electrodes connecting the wirings of the Nth level and wirings N−1th level by a series of process steps, and embeds a wiring metal such as copper into these recesses, thereby to form the wirings and the electrodes at the same time.
With the minaturization of circuit patterns, there has been proposed a process that: employs a three-layered resist including a photomask, an SOG film (i.e., an SiO2 film formed by a spin coating process) and an organic film which are stacked in that order; forms holes, corresponding to via holes, in an interlayer insulating film in which the organic film is filled; and utilizes the organic film as an etch mask to form trenches, and then removes the organic film to form recesses including the trenches and the via holes.
In the above method, a spin coating process is employed in order to form each of the photomask, the SOG film and the organic film. During formation of such a coating film by the spin coating process, a large amount of a coating liquid containing a raw material of the coating film is supplied to a rotating substrate, and a considerably large part of the supplied coating liquid is spun off due to centrifugal force and spreads around the substrate. Thus, the foregoing process is costly and the throughput thereof is low, since a large number of process steps are necessary.
In order to solve the above problem, the use of a layered structure 1 having a constitution shown in FIG. 6 is considered. In this case (the following will be described again in detail in the description of the embodiments of the invention), holes 10 are firstly formed by etching an SiO2 (silicon oxide) film 14 (interlayer insulating film) via films from an antireflective film 17 to an SiN film 15 by using a resist pattern 18a formed in a photoresist (PR) film (hereinafter referred simply as “resist film”) as a mask. Next, the holes 10 are extended into an underlying organic film 13; then the pattern of the SiO2 film 16 is transferred to an SiN (silicon nitride) film 15; and then trenches are formed in the SiO2 film 14, and concurrently, holes are formed in an SiOCH film 12 (low-k film) by using the SiN film 15 as a mask, thereby to form trenches and via holes.
The above method is advantageous in that it costs lower, and in that the number of the process steps is smaller and thus the throughput is higher, as compared with the foregoing method using three-layered resist. When performing this method, it is preferable to etch the layered films from the antireflective film 17 to the SiO2 film 14 in one process step to form the holes. However, if such an etching process is performed, strongly etched areas appear in the hole locally with respect to the circumferential direction thereof, which is called “striation” (vertical steak). FIG. 7(a) shows the upper surface of the layered structure 1 after etching the SiO2 film 14, and FIG. 7(b) is a cross-sectional view of a part of the layered structure 1. In these figures, 10a designates the striation. The development of striations is resulted from the fact that the etch rates of the resist film 18, the antireflective film 17, the SiO2 films 14, 16 and the SiN film 15 by the etching gas converted into plasma are different from each other.
That is, as shown in FIGS. 8(a) and (b), as etching of the SiO2 film 14 progresses, the films are etched so that the diameter of the hole increases in such a manner that the diameter of the hole is wider according to the proximity to the upper end of the hole. If the difference in etch rates between adjacent films is large, in other words, etch selectivity between the adjacent films exists, the hole diameter increasing rates of adjacent films are different from one another and thus a step is formed at the interface between the adjacent films. In addition, although the thickness of each film is specified by the specification of the semiconductor device, the actual film thickness is not completely uniform. As a result, the hole diameter increasing rate is different in different circumferential areas of the hole, and thus the size of the step between adjacent films is different in different circumferential areas of the hole. Accordingly, the films above the SiO2 film 14 are locally etched strongly so that the shape of the holes in the films above the SiO2 film 14 is distorted, and the distorted shape of the hole in the film overlying the SiO2 film 14 is transferred to the SiO2 film 14, whereby the striations are developed.
The lithography process is performed such that the pattern for the SiO2 film 16 and the pattern for the SiO2 film 14 are aligned. However, misalignment may possibly occur. If minaturization of the pattern further progresses in the future, some degree of misalignment can not be avoided. In a case where the line width of the pattern for the SiO2 film 16 is close to that for the resist film 18, misalignment is likely to occur. In this case, as the pattern for the SiO2 film 16 and that for the resist film 18 partially overlaps, the SiO2 film 16 partially exposed at a part of the circumference of the hole when etching the antireflective film 16, as shown in FIG. 9. As a result, non-uniformity of the etch amount of the sidewall of the hole is increased, and thus the striations are more likely to be developed. The aforementioned problem should be solved to conduct the foregoing dual damascene process at a low cost.
JP2005-243978A teaches, in paragraph [0025] thereof, that a mixed gas of CF4 gas and O2 gas may be used for concurrently etching a resist film and an underlying SiO2 interlayer insulating film at the essentially the same etch rate. However, JP2005-243978A fails to disclose or suggest a mixed gas for concurrently etching a multilayered structure including not only a resist film and an SiO2 film but also inorganic sacrifice films, which is one of the remarkable features of the present invention.